1. Field of Invention
The present invention relates to a matrix decoder. More particularly, the present invention relates to a matrix decoder including level shifters.
2. Description of Related Art
FIG. 1 is a schematic block diagram of a conventional gate driver 100 which is applicable to a liquid crystal display panel. The decoder 101 has a plurality of output terminals, each output terminal is coupled with a level shifter and an output stage and is eventually coupled to one of the gate lines G1˜Gm.
The decoder 101 receives control signals X0˜Xn, and the control signals X0˜Xn indicate which gate line is to be turned on. For example, if the gate line G1 is to be turned on, the decoder 101 outputs logic 1 to the level shifter 102 and logic 0 to the other level shifters after decoding the control signals X0˜Xn. Next, each of the level shifters boosts the voltage of the input signal to the voltage required by high voltage component, and then outputs the boosted signal to the corresponding output stage, so that the gate line G1 is turned on because of logic 1 and the other gate lines are turned off because of logic 0.
The aforementioned decoder 101 is formed by low voltage components; the level shifters 102 include low, middle, and high voltage components, wherein most components are high voltage components; and the output stages 103 all use high voltage components. Since the level shifters and the output stages require high voltage process, and the numbers thereof are the same as that of the output terminals of the gate driver, the surface area of the conventional gate driver cannot be reduced due to the large number of high voltage metal oxide semiconductor field effect transistors (MOSFETs).